Modeling and Analysis of The Difference-Bit Cache

Advances in VLSI technology and processor architectures have resulted in a tremendous increase in processor speeds and memory capacities. However memory latencies have failed to improve as rapidly, making memory systems the performance limiters in most high performance processor architectures. Caching is a time-tested mechanism to solve this speed disparity. Among the different cache mapping organizations, direct mapping is the only configuration where the critical path is merely the time requried to access a RAM. Although direct mapped caches are preferable considering hit-access times, they have poor hit ratios compared to associative caches. The difference-bit cache proposed by Lang et al [1] is functionally equivalent to a two-way set-associative cache but tries to achieve an access time smaller than that of a conventional two-way set-associative cache and close to that of a direct-mapped cache. We modeled and implemented the difference-bit cache to prove the hypothesis of its small access time. We have also tried to prove that the access time advantage of the difference-bit cache improves over the conventional two-way set-associative cache with an increase in the cache size. Finally we have tried to analyze the trade-offs involved in applying these techniques to a higher associativity cache.